💻New Paper Closes Deployment Gap for PLC Formal Verification
Formal verification gets a hardware reality check
TL;DR
A new paper presents hardware-faithful verification for IEC 61131-3 on open hardware, closing the deployment gap. It uses a declarative HAL descriptor to describe hardware and constrains inputs to realizable ranges.
The ESBMC-Arduino paper submitted on July 9, 2026, tackles the issue of formal verification for IEC 61131-3 on open-hardware PLCs. Existing verifiers prove safety over an abstract model but fail in real-world scenarios due to hardware constraints like finite-resolution ADC and resource-constrained MCUs. The paper introduces a declarative HAL descriptor that describes hardware accurately, ensuring robustness proofs while eliminating false alarms. This is crucial for developers working on embedded systems where precision matters.
Key Points
Paper title: 'ESBMC-Arduino: Closing the Deployment Gap for Formal Verification of Open-Hardware PLCs'
Authors: Pierre Dantas, Lucas Cordeiro, and Waldir Junior
Abstract available on arXiv with DOI: 10.48550/arXiv.2607.08550
Paper published in PDF format, 21 pages long
Cited by NASA ADS, Google Scholar, and Semantic Scholar
Why It Matters
If you're working on embedded systems with IEC 61131-3 PLCs, this paper is a must-read. It bridges the gap between abstract models and real-world hardware constraints, ensuring more accurate verification without false alarms.
Frequently Asked Questions
Why does this matter?
If you're working on embedded systems with IEC 61131-3 PLCs, this paper is a must-read. It bridges the gap between abstract models and real-world hardware constraints, ensuring more accurate verification without false alarms.
What happened?
A new paper presents hardware-faithful verification for IEC 61131-3 on open hardware, closing the deployment gap. It uses a declarative HAL descriptor to describe hardware and constrains inputs to realizable ranges.
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