💡XCENA's Chip Cuts AI Infrastructure Costs by Placing Compute Near Memory
AI workloads could get cheaper with XCENA's new chip design
TL;DR
XCENA raised $135 million to develop a chip that places compute near memory, potentially reducing AI infrastructure costs. The MX1 chip connects via CXL and could make routine data operations more efficient.
XCENA just raised $135M in Series B funding for its MX1 chip, which aims to reduce the cost of running AI workloads by placing compute capabilities closer to DRAM. This approach cuts down on expensive round trips between memory and CPUs/GPUs, a bottleneck in current systems. If successful, XCENA's solution could significantly lower costs for hyperscalers spending billions annually on AI infrastructure. The MX1 chip is set to roll off Samsung’s foundry lines by the end of 2026.

Key Points
XCENA's MX1 chip connects via CXL and processes data before leaving the memory module, reducing costly round trips.
$135M Series B funding brings XCENA’s total raised to $185M at a valuation of $570 million.
MX1 has thousands of cores compared to Marvell's handful of general-purpose cores in their approach.
XCENA is targeting hyperscalers spending tens of billions annually on AI infrastructure, with talks ongoing with memory vendors.
Mass production chips are scheduled for late 2026, with revenue expected starting in 2027.
Why It Matters
If you're a hyperscaler running massive AI workloads, XCENA's MX1 chip could cut costs by placing compute near DRAM. This reduces the need for expensive round trips between memory and CPUs/GPUs, potentially saving billions annually.
Frequently Asked Questions
Why does this matter?
If you're a hyperscaler running massive AI workloads, XCENA's MX1 chip could cut costs by placing compute near DRAM. This reduces the need for expensive round trips between memory and CPUs/GPUs, potentially saving billions annually.
What happened?
XCENA raised $135 million to develop a chip that places compute near memory, potentially reducing AI infrastructure costs. The MX1 chip connects via CXL and could make routine data operations more efficient.
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