
New Paper Closes Deployment Gap for PLC Formal Verification
The ESBMC-Arduino paper submitted on July 9, 2026, tackles the issue of formal verification for IEC 61131-3 on open-hardware PLCs. Existing verifiers prove safety over an abstract model but fail in real-world scenarios due to hardware constraints like finite-resolution ADC and resource-constrained MCUs. The paper introduces a declarative HAL descriptor that describes hardware accurately, ensuring robustness proofs while eliminating false alarms. This is crucial for developers working on embedded systems where precision matters.








